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IR3841MPbF
Thermal Shutdown
Temperature sensing is provided inside IR3841.
The trip threshold is typically set to 140 o C. When
1.5V <Vin<16V
4.5V <Vcc<5.5V
trip threshold is exceeded, thermal shutdown
turns off both MOSFETs and discharges the soft
start capacitor.
Automatic restart is initiated when the sensed
temperature drops within the operating range.
PGood
Vcc
PGood
Seq
Rt
Enable
Vin
Boot
SW
OCSet
Fb
RA
RB
Vo(master)
There is a 20 o C hysteresis in the thermal
shutdown threshold.
SS/ SD
Gnd
PGnd
Comp
Output Voltage Sequencing
The IR3841 can accommodate user
programmable sequencing options using Seq,
1.5V <Vin<16V
4.5V <Vcc<5.5V
Enable and Power Good pins.
Enable
Vin
Boot
Vo(master)
Vcc
SW
Vo(slave)
PGood
Vo1
RE
PGood
OCSet
RC
Seq
Fb
Vo2
RF
Rt
RD
SS/ SD
Gnd
PGnd
Comp
Simultaneous Powerup
Fig. 8b. Application Circuit for Simultaneous
Fig. 8a. Simultaneous Power-up of the slave
Sequencing
with respect to the master.
Power Good Output
Through these pins, voltage sequencing such as
simultaneous and sequential can be
implemented. Figure 8. shows simultaneous
sequencing configurations. In simultaneous
power-up, the voltage at the Seq pin of the slave
reaches 0.7V before the Fb pin of the master. For
R E /R F =R C /R D , therefore, the output voltage of
the slave follows that of the master until the
voltage at the Seq pin of the slave reaches 0.7 V.
After the voltage at the Seq pin of the slave
exceeds 0.85V, the internal 0.7V reference of
the slave dictates its output voltage.
06/18/09
The IC continually monitors the output voltage via
Feedback (Fb pin). The feedback voltage is
compared to a fixed voltage. As soon as the Fb
voltage reaches 0.88* V ref , the Power Good signal
flags. This pin is open drain and it needs to be
externally pulled high. High state indicates that
output is in regulation. Fig 9. shows the timing
diagram for the PGood function.
14
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